Technical Field
This relates generally to a method, apparatus and system for an edge rate controlled output buffer.
Description of Related Art
Traditionally, low power and low voltage edge rate controlled buffers are inverter based output buffers. Such buffers tend to have high current peak due to shoot-through current, inductive supply noise due to large voltage drop, and electromagnetic interference (EMI) due to high output edge switching rates.
It is also challenging to control edge rate over PVT, due to non-linear edge rate behavior that is variable over process, voltage and temperature (PVT). Current approaches show input current signal dependent propagation delay, which creates large and unexpected mismatch between falling and rising transition.
FIG. 1 depicts a prior art approach using inverter staggered type edge rate. In such an approach, a precise clock scheme is needed to control accurate edge rate. In addition, the open-loop approach of FIG. 1 is not suitable for large load change requirement, because it is difficult to have load independent control. As a result, the edge rate varies not only input control signal, but also capacitive load.
FIG. 2 depicts another prior art approach to implement for input current, TIN1 and IIN2. Utilizing a simple feedback based buffer and having large Cdg non-linear capacitance of MP and MN causes the slope to be non-linear with a constant input signal. Hence, a large feedback capacitor (CF>>Cdg) must be used along with the large input current signal. This requires silicon large area and often creates large propagation delay in order to drive a large linear feedback capacitor CF. Since there is no direct charge initialization of the feedback capacitor CF, the startup voltage mismatch between the drivers (MP or MN) and the feedback initial voltage creates signal dependent propagation delay. This signal dependent delay will cause the crossing point distortion in an eye diagram test. As a result, the approach of FIG. 2 is unable to accurately initialize feedback capacitance over PVT in order to achieve signal insensitive propagation delay.
Therefore, there is a need for an accurate and improved control edge rate control over process, voltage and temperature that minimizes signal dependent startup time in order to achieve good signal integrity.